Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100274368	1			T1	64873		T2	235		T13	162717
all_values[1]	100274368	1			T1	64873		T2	235		T13	162717
all_values[2]	100274368	1			T1	64873		T2	235		T13	162717

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

536607

1

T1

2465

T2

8

T13

16

auto[1]

300286497

1

T1

192154

T2

697

T13

488135

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299293464

1

T1

193464

T2

600

T13

486747

auto[1]

1529640

1

T1

1155

T2

105

T13

1404

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	171475	1			T1	624		T2	6		T15	1772
all_values[0]	auto[0]	auto[1]	2148	1			T1	8		T2	2		T15	30
all_values[0]	auto[1]	auto[0]	99593013	1			T1	63864		T2	194		T13	162249
all_values[0]	auto[1]	auto[1]	507732	1			T1	377		T2	33		T13	468
all_values[1]	auto[0]	auto[0]	171948	1			T1	1253		T13	11		T15	4409
all_values[1]	auto[0]	auto[1]	1602	1			T1	12		T13	5		T15	24
all_values[1]	auto[1]	auto[0]	99592540	1			T1	63235		T2	200		T13	162238
all_values[1]	auto[1]	auto[1]	508278	1			T1	373		T2	35		T13	463
all_values[2]	auto[0]	auto[0]	187823	1			T1	560		T15	369		T17	2675
all_values[2]	auto[0]	auto[1]	1611	1			T1	8		T15	8		T17	8
all_values[2]	auto[1]	auto[0]	99576665	1			T1	63928		T2	200		T13	162249
all_values[2]	auto[1]	auto[1]	508269	1			T1	377		T2	35		T13	468