Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
347902 |
1 |
|
|
T1 |
460 |
|
T2 |
2 |
|
T13 |
620 |
auto[1] |
345708 |
1 |
|
|
T1 |
152 |
|
T2 |
46 |
|
T14 |
74 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173146 |
1 |
|
|
T1 |
142 |
|
T2 |
13 |
|
T13 |
158 |
lower_val |
171938 |
1 |
|
|
T1 |
154 |
|
T2 |
12 |
|
T13 |
152 |
zero_val |
1785 |
1 |
|
|
T1 |
7 |
|
T2 |
1 |
|
T13 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
347646 |
1 |
|
|
T1 |
304 |
|
T2 |
28 |
|
T13 |
314 |
lower_val |
345960 |
1 |
|
|
T1 |
308 |
|
T2 |
20 |
|
T13 |
306 |
zero_val |
4 |
1 |
|
|
T140 |
2 |
|
T141 |
2 |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val , lower_val] |
[zero_val] |
[auto[0]] |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43171 |
1 |
|
|
T1 |
57 |
|
T13 |
74 |
|
T14 |
1 |
higher_val |
higher_val |
auto[1] |
43566 |
1 |
|
|
T1 |
15 |
|
T2 |
6 |
|
T14 |
6 |
higher_val |
lower_val |
auto[0] |
43311 |
1 |
|
|
T1 |
54 |
|
T2 |
1 |
|
T13 |
84 |
higher_val |
lower_val |
auto[1] |
43097 |
1 |
|
|
T1 |
16 |
|
T2 |
6 |
|
T14 |
15 |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T140 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
43258 |
1 |
|
|
T1 |
61 |
|
T13 |
79 |
|
T15 |
46 |
lower_val |
higher_val |
auto[1] |
42801 |
1 |
|
|
T1 |
20 |
|
T2 |
6 |
|
T14 |
7 |
lower_val |
lower_val |
auto[0] |
43181 |
1 |
|
|
T1 |
50 |
|
T13 |
73 |
|
T15 |
44 |
lower_val |
lower_val |
auto[1] |
42697 |
1 |
|
|
T1 |
23 |
|
T2 |
6 |
|
T14 |
5 |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T141 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
676 |
1 |
|
|
T1 |
3 |
|
T13 |
1 |
|
T14 |
1 |
zero_val |
higher_val |
auto[1] |
213 |
1 |
|
|
T1 |
1 |
|
T15 |
3 |
|
T17 |
1 |
zero_val |
lower_val |
auto[0] |
670 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T15 |
4 |
zero_val |
lower_val |
auto[1] |
226 |
1 |
|
|
T15 |
4 |
|
T17 |
3 |
|
T142 |
2 |