Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100274368	1			T1	64873		T2	235		T13	162717
all_pins[1]	100274368	1			T1	64873		T2	235		T13	162717
all_pins[2]	100274368	1			T1	64873		T2	235		T13	162717

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300024789	1			T1	188073		T2	672		T13	487683
values[0x1]	798315	1			T1	6546		T2	33		T13	468
transitions[0x0=>0x1]	796540	1			T1	6508		T2	33		T13	468
transitions[0x1=>0x0]	796576	1			T1	6508		T2	33		T13	468

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99766636	1			T1	64496		T2	202		T13	162249
all_pins[0]	values[0x1]	507732	1			T1	377		T2	33		T13	468
all_pins[0]	transitions[0x0=>0x1]	507726	1			T1	377		T2	33		T13	468
all_pins[0]	transitions[0x1=>0x0]	83	1			T19	4		T157	6		T158	2
all_pins[1]	values[0x0]	100274279	1			T1	64873		T2	235		T13	162717
all_pins[1]	values[0x1]	89	1			T19	4		T157	6		T158	2
all_pins[1]	transitions[0x0=>0x1]	74	1			T19	4		T157	6		T158	2
all_pins[1]	transitions[0x1=>0x0]	290479	1			T1	6169		T15	3290		T17	5901
all_pins[2]	values[0x0]	99983874	1			T1	58704		T2	235		T13	162717
all_pins[2]	values[0x1]	290494	1			T1	6169		T15	3290		T17	5901
all_pins[2]	transitions[0x0=>0x1]	288740	1			T1	6131		T15	3269		T17	5862
all_pins[2]	transitions[0x1=>0x0]	506014	1			T1	339		T2	33		T13	468