Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	633	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5542	1			T1	30		T14	6		T15	53
len_601_800	12465	1			T1	58		T14	9		T15	113
len_401_600	8448	1			T1	50		T14	5		T15	89
len_201_400	16506	1			T1	22		T14	3		T15	52
len_65_200	73678	1			T1	34		T2	14		T15	38
len_min_for_xof_require_squeeze	1008	1			T17	1		T18	10		T19	1
len_keccak_block_sizes[72]	749	1			T1	2		T18	5		T67	9
len_keccak_block_sizes[104]	750	1			T18	5		T67	9		T173	1
len_keccak_block_sizes[136]	751	1			T15	1		T18	5		T67	9
len_keccak_block_sizes[144]	277	1			T2	1		T15	1		T18	5
len_keccak_block_sizes[168]	279	1			T18	5		T174	5		T175	5
len_datapath_width	13990	1			T1	9		T2	2		T15	17
len_2_63	214358	1			T1	99		T2	8		T13	310
len_1	52	1			T17	1		T176	1		T177	1