Summary for Variable share
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for share
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 10747153 | 1 |  |  | T1 | 33731 |  | T2 | 929 |  | T13 | 3720 | 
| auto[1] | 25740455 | 1 |  |  | T1 | 52300 |  | T2 | 1614 |  | T13 | 15500 | 
Summary for Variable state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 4 | 0 | 4 | 100.00 | 
User Defined Bins for state_read_mask
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| word_access | 36368343 | 1 |  |  | T1 | 85868 |  | T2 | 2529 |  | T13 | 19220 | 
| triple_byte_access | 39675 | 1 |  |  | T1 | 50 |  | T2 | 4 |  | T14 | 8 | 
| halfword_access | 39787 | 1 |  |  | T1 | 55 |  | T2 | 5 |  | T14 | 5 | 
| byte_access | 39803 | 1 |  |  | T1 | 58 |  | T2 | 5 |  | T14 | 4 | 
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 8 | 3 | 5 | 62.50 | 3 | 
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
| share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS | 
| [auto[1]] | [triple_byte_access , halfword_access , byte_access] | -- | -- | 3 |  | 
Covered bins
| share | state_read_mask | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | word_access | 10627888 | 1 |  |  | T1 | 33568 |  | T2 | 915 |  | T13 | 3720 | 
| auto[0] | triple_byte_access | 39675 | 1 |  |  | T1 | 50 |  | T2 | 4 |  | T14 | 8 | 
| auto[0] | halfword_access | 39787 | 1 |  |  | T1 | 55 |  | T2 | 5 |  | T14 | 5 | 
| auto[0] | byte_access | 39803 | 1 |  |  | T1 | 58 |  | T2 | 5 |  | T14 | 4 | 
| auto[1] | word_access | 25740455 | 1 |  |  | T1 | 52300 |  | T2 | 1614 |  | T13 | 15500 |