Group : kmac_env_pkg::kmac_env_cov::state_read_mask_cg
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Group : kmac_env_pkg::kmac_env_cov::state_read_mask_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
78.57 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 6 0 6 100.00
Crosses 8 3 5 62.50


Variables for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
share 2 0 2 100.00 100 1 1 2
state_read_mask 4 0 4 100.00 100 1 1 0


Crosses for Group kmac_env_pkg::kmac_env_cov::state_read_mask_cg
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
state_mask_share_cross 8 3 5 62.50 100 1 1 0


Summary for Variable share

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for share

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 10747153 1 T1 33731 T2 929 T13 3720
auto[1] 25740455 1 T1 52300 T2 1614 T13 15500



Summary for Variable state_read_mask

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for state_read_mask

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
word_access 36368343 1 T1 85868 T2 2529 T13 19220
triple_byte_access 39675 1 T1 50 T2 4 T14 8
halfword_access 39787 1 T1 55 T2 5 T14 5
byte_access 39803 1 T1 58 T2 5 T14 4



Summary for Cross state_mask_share_cross

Samples crossed: share state_read_mask
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 8 3 5 62.50 3


Automatically Generated Cross Bins for state_mask_share_cross

Uncovered bins
sharestate_read_maskCOUNTAT LEASTNUMBERSTATUS
[auto[1]] [triple_byte_access , halfword_access , byte_access] -- -- 3


Covered bins
sharestate_read_maskCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] word_access 10627888 1 T1 33568 T2 915 T13 3720
auto[0] triple_byte_access 39675 1 T1 50 T2 4 T14 8
auto[0] halfword_access 39787 1 T1 55 T2 5 T14 5
auto[0] byte_access 39803 1 T1 58 T2 5 T14 4
auto[1] word_access 25740455 1 T1 52300 T2 1614 T13 15500

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