Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	101461137	1			T1	1898		T2	6102		T3	16449
all_values[1]	101461137	1			T1	1898		T2	6102		T3	16449
all_values[2]	101461137	1			T1	1898		T2	6102		T3	16449

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

551660

1

T1

100

T2

957

T3

740

auto[1]

303831751

1

T1

5594

T2

17349

T3

48607

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

302850981

1

T1

5178

T2

18138

T3

48840

auto[1]

1532430

1

T1

516

T2

168

T3

507

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	197033	1			T1	8		T2	317		T3	235
all_values[0]	auto[0]	auto[1]	2016	1			T1	2		T2	2		T3	2
all_values[0]	auto[1]	auto[0]	100753294	1			T1	1718		T2	5729		T3	16045
all_values[0]	auto[1]	auto[1]	508794	1			T1	170		T2	54		T3	167
all_values[1]	auto[0]	auto[0]	149873	1			T1	32		T2	317		T3	235
all_values[1]	auto[0]	auto[1]	1432	1			T1	3		T2	2		T3	2
all_values[1]	auto[1]	auto[0]	100800454	1			T1	1694		T2	5729		T3	16045
all_values[1]	auto[1]	auto[1]	509378	1			T1	169		T2	54		T3	167
all_values[2]	auto[0]	auto[0]	199703	1			T1	50		T2	317		T3	263
all_values[2]	auto[0]	auto[1]	1603	1			T1	5		T2	2		T3	3
all_values[2]	auto[1]	auto[0]	100750624	1			T1	1676		T2	5729		T3	16017
all_values[2]	auto[1]	auto[1]	509207	1			T1	167		T2	54		T3	166