Group : kmac_env_pkg::kmac_env_cov::msg_len_cg
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Group : kmac_env_pkg::kmac_env_cov::msg_len_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv



Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 15 0 15 100.00


Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
msg_len 15 0 15 100.00 100 1 1 0


Summary for Variable msg_len

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 15 0 15 100.00


User Defined Bins for msg_len

Excluded/Illegal bins
NAMECOUNTSTATUS
remainder 10352 Excluded


Covered bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
len_7501_10000 9146 1 T1 26 T12 19 T14 30
len_5001_7500 14621 1 T1 45 T12 18 T14 30
len_2501_5000 9337 1 T1 16 T12 18 T14 30
len_1025_2500 5464 1 T1 10 T12 11 T14 16
len_769_1024 6212 1 T1 1 T2 9 T3 30
len_513_768 6670 1 T1 2 T2 11 T3 31
len_257_512 21172 1 T1 2 T2 7 T3 21
len_0_256 257357 1 T1 11 T2 11 T3 23
len_keccak_block_sizes[72] 717 1 T12 2 T13 1 T14 3
len_keccak_block_sizes[104] 630 1 T12 2 T14 3 T17 3
len_keccak_block_sizes[136] 522 1 T12 2 T14 3 T17 3
len_keccak_block_sizes[144] 423 1 T3 1 T14 3 T17 3
len_keccak_block_sizes[168] 325 1 T14 3 T17 3 T18 3
len_1 763 1 T12 2 T14 3 T17 3
len_0 1241 1 T1 3 T12 2 T14 3

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