Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	101461137	1			T1	1898		T2	6102		T3	16449
all_pins[1]	101461137	1			T1	1898		T2	6102		T3	16449
all_pins[2]	101461137	1			T1	1898		T2	6102		T3	16449

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	303607220	1			T1	5522		T2	18252		T3	49180
values[0x1]	776191	1			T1	172		T2	54		T3	167
transitions[0x0=>0x1]	774533	1			T1	172		T2	54		T3	167
transitions[0x1=>0x0]	774565	1			T1	172		T2	54		T3	167

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100952343	1			T1	1728		T2	6048		T3	16282
all_pins[0]	values[0x1]	508794	1			T1	170		T2	54		T3	167
all_pins[0]	transitions[0x0=>0x1]	508783	1			T1	170		T2	54		T3	167
all_pins[0]	transitions[0x1=>0x0]	59	1			T1	2		T160	2		T161	6
all_pins[1]	values[0x0]	101461067	1			T1	1896		T2	6102		T3	16449
all_pins[1]	values[0x1]	70	1			T1	2		T160	2		T161	6
all_pins[1]	transitions[0x0=>0x1]	57	1			T1	2		T160	2		T161	6
all_pins[1]	transitions[0x1=>0x0]	267314	1			T21	8650		T22	315		T23	4913
all_pins[2]	values[0x0]	101193810	1			T1	1898		T2	6102		T3	16449
all_pins[2]	values[0x1]	267327	1			T21	8650		T22	315		T23	4913
all_pins[2]	transitions[0x0=>0x1]	265693	1			T21	8594		T22	314		T23	4879
all_pins[2]	transitions[0x1=>0x0]	507192	1			T1	170		T2	54		T3	167