Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	621	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5732	1			T1	20		T2	9		T3	30
len_601_800	12748	1			T1	43		T2	15		T3	35
len_401_600	8378	1			T1	25		T2	8		T3	23
len_201_400	16497	1			T1	6		T2	5		T3	11
len_65_200	73601	1			T1	5		T3	3		T13	5
len_min_for_xof_require_squeeze	1002	1			T1	1		T13	1		T14	9
len_keccak_block_sizes[72]	747	1			T14	9		T17	9		T18	5
len_keccak_block_sizes[104]	744	1			T14	9		T17	9		T18	5
len_keccak_block_sizes[136]	748	1			T14	9		T17	9		T18	5
len_keccak_block_sizes[144]	280	1			T18	5		T66	5		T131	1
len_keccak_block_sizes[168]	278	1			T18	5		T66	5		T24	1
len_datapath_width	14042	1			T2	1		T14	9		T17	9
len_2_63	214391	1			T1	10		T2	33		T3	45
len_1	44	1			T175	1		T176	2		T177	1