Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100177747	1			T1	1494		T2	284		T3	12755
all_values[1]	100177747	1			T1	1494		T2	284		T3	12755
all_values[2]	100177747	1			T1	1494		T2	284		T3	12755

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

551214

1

T1

80

T2

12

T3

2432

auto[1]

299982027

1

T1

4402

T2

840

T3

35833

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299004747

1

T1

4440

T2

810

T3

37011

auto[1]

1528494

1

T1

42

T2

42

T3

1254

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	192784	1			T2	4		T3	620		T14	5
all_values[0]	auto[0]	auto[1]	1962	1			T2	2		T3	30		T14	6
all_values[0]	auto[1]	auto[0]	99475465	1			T1	1480		T2	266		T3	11717
all_values[0]	auto[1]	auto[1]	507536	1			T1	14		T2	12		T3	388
all_values[1]	auto[0]	auto[0]	173773	1			T3	1504		T14	1		T17	21
all_values[1]	auto[0]	auto[1]	1536	1			T3	37		T14	2		T17	4
all_values[1]	auto[1]	auto[0]	99494476	1			T1	1480		T2	270		T3	10833
all_values[1]	auto[1]	auto[1]	507962	1			T1	14		T2	14		T3	381
all_values[2]	auto[0]	auto[0]	179628	1			T1	79		T2	4		T3	233
all_values[2]	auto[0]	auto[1]	1531	1			T1	1		T2	2		T3	8
all_values[2]	auto[1]	auto[0]	99488621	1			T1	1401		T2	266		T3	12104
all_values[2]	auto[1]	auto[1]	507967	1			T1	13		T2	12		T3	410