Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
374900 |
1 |
|
|
T1 |
32 |
|
T2 |
18 |
|
T3 |
282 |
auto[1] |
317906 |
1 |
|
|
T3 |
300 |
|
T17 |
392 |
|
T18 |
62 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173876 |
1 |
|
|
T1 |
8 |
|
T3 |
145 |
|
T14 |
1142 |
lower_val |
171771 |
1 |
|
|
T1 |
10 |
|
T2 |
4 |
|
T3 |
131 |
zero_val |
1799 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
10 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
346094 |
1 |
|
|
T1 |
12 |
|
T2 |
12 |
|
T3 |
306 |
lower_val |
346698 |
1 |
|
|
T1 |
20 |
|
T2 |
6 |
|
T3 |
276 |
zero_val |
14 |
1 |
|
|
T156 |
2 |
|
T157 |
2 |
|
T158 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
46938 |
1 |
|
|
T1 |
4 |
|
T3 |
33 |
|
T14 |
563 |
higher_val |
higher_val |
auto[1] |
39624 |
1 |
|
|
T3 |
40 |
|
T17 |
42 |
|
T18 |
9 |
higher_val |
lower_val |
auto[0] |
47147 |
1 |
|
|
T1 |
4 |
|
T3 |
35 |
|
T14 |
579 |
higher_val |
lower_val |
auto[1] |
40164 |
1 |
|
|
T3 |
37 |
|
T17 |
56 |
|
T18 |
7 |
higher_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T158 |
1 |
|
T159 |
1 |
|
- |
- |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T160 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
46264 |
1 |
|
|
T1 |
4 |
|
T2 |
3 |
|
T3 |
35 |
lower_val |
higher_val |
auto[1] |
39429 |
1 |
|
|
T3 |
38 |
|
T17 |
40 |
|
T18 |
8 |
lower_val |
lower_val |
auto[0] |
46521 |
1 |
|
|
T1 |
6 |
|
T2 |
1 |
|
T3 |
29 |
lower_val |
lower_val |
auto[1] |
39554 |
1 |
|
|
T3 |
29 |
|
T17 |
44 |
|
T18 |
5 |
lower_val |
zero_val |
auto[1] |
3 |
1 |
|
|
T156 |
1 |
|
T161 |
2 |
|
- |
- |
zero_val |
higher_val |
auto[0] |
663 |
1 |
|
|
T2 |
1 |
|
T3 |
5 |
|
T14 |
2 |
zero_val |
higher_val |
auto[1] |
214 |
1 |
|
|
T3 |
1 |
|
T18 |
1 |
|
T19 |
2 |
zero_val |
lower_val |
auto[0] |
716 |
1 |
|
|
T1 |
1 |
|
T3 |
1 |
|
T14 |
3 |
zero_val |
lower_val |
auto[1] |
206 |
1 |
|
|
T3 |
3 |
|
T24 |
2 |
|
T162 |
9 |