Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100177747	1			T1	1494		T2	284		T3	12755
all_pins[1]	100177747	1			T1	1494		T2	284		T3	12755
all_pins[2]	100177747	1			T1	1494		T2	284		T3	12755

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	299704709	1			T1	4468		T2	840		T3	34703
values[0x1]	828532	1			T1	14		T2	12		T3	3562
transitions[0x0=>0x1]	826544	1			T1	14		T2	12		T3	3538
transitions[0x1=>0x0]	826577	1			T1	14		T2	12		T3	3538

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99670211	1			T1	1480		T2	272		T3	12367
all_pins[0]	values[0x1]	507536	1			T1	14		T2	12		T3	388
all_pins[0]	transitions[0x0=>0x1]	507520	1			T1	14		T2	12		T3	388
all_pins[0]	transitions[0x1=>0x0]	64	1			T171	7		T172	3		T173	6
all_pins[1]	values[0x0]	100177667	1			T1	1494		T2	284		T3	12755
all_pins[1]	values[0x1]	80	1			T171	7		T172	3		T173	6
all_pins[1]	transitions[0x0=>0x1]	71	1			T171	7		T172	3		T173	6
all_pins[1]	transitions[0x1=>0x0]	320907	1			T3	3174		T23	7532		T24	15506
all_pins[2]	values[0x0]	99856831	1			T1	1494		T2	284		T3	9581
all_pins[2]	values[0x1]	320916	1			T3	3174		T23	7532		T24	15506
all_pins[2]	transitions[0x0=>0x1]	318953	1			T3	3150		T23	7477		T24	15397
all_pins[2]	transitions[0x1=>0x0]	505606	1			T1	14		T2	12		T3	364