Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100797376	1			T1	283040		T2	158532		T11	284384
all_values[1]	100797376	1			T1	283040		T2	158532		T11	284384
all_values[2]	100797376	1			T1	283040		T2	158532		T11	284384

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

620412

1

T1

4451

T2

3

T11

5077

auto[1]

301771716

1

T1

844669

T2

475593

T11

848075

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

300861927

1

T1

848259

T2

474156

T11

852327

auto[1]

1530201

1

T1

861

T2

1440

T11

825

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	205944	1			T1	4445		T2	1		T12	66
all_values[0]	auto[0]	auto[1]	2174	1			T1	6		T2	2		T12	2
all_values[0]	auto[1]	auto[0]	100081365	1			T1	278308		T2	158051		T11	284109
all_values[0]	auto[1]	auto[1]	507893	1			T1	281		T2	478		T11	275
all_values[1]	auto[0]	auto[0]	191439	1			T11	3715		T12	66		T14	3
all_values[1]	auto[0]	auto[1]	1702	1			T11	4		T12	2		T14	4
all_values[1]	auto[1]	auto[0]	100095870	1			T1	282753		T2	158052		T11	280394
all_values[1]	auto[1]	auto[1]	508365	1			T1	287		T2	480		T11	271
all_values[2]	auto[0]	auto[0]	217485	1			T11	1357		T13	5		T15	2
all_values[2]	auto[0]	auto[1]	1668	1			T11	1		T13	1		T15	1
all_values[2]	auto[1]	auto[0]	100069824	1			T1	282753		T2	158052		T11	282752
all_values[2]	auto[1]	auto[1]	508399	1			T1	287		T2	480		T11	274