Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
323734 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T4 |
2 |
auto[1] |
370584 |
1 |
|
|
T1 |
356 |
|
T2 |
618 |
|
T11 |
346 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
174212 |
1 |
|
|
T1 |
84 |
|
T2 |
149 |
|
T11 |
86 |
lower_val |
171573 |
1 |
|
|
T1 |
92 |
|
T2 |
162 |
|
T11 |
74 |
zero_val |
1823 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T4 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
348028 |
1 |
|
|
T1 |
178 |
|
T2 |
322 |
|
T11 |
162 |
lower_val |
346280 |
1 |
|
|
T1 |
180 |
|
T2 |
298 |
|
T4 |
2 |
zero_val |
10 |
1 |
|
|
T150 |
2 |
|
T151 |
2 |
|
T152 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
40519 |
1 |
|
|
T2 |
1 |
|
T12 |
12 |
|
T15 |
51 |
higher_val |
higher_val |
auto[1] |
46580 |
1 |
|
|
T1 |
40 |
|
T2 |
75 |
|
T11 |
37 |
higher_val |
lower_val |
auto[0] |
40545 |
1 |
|
|
T12 |
2 |
|
T13 |
2 |
|
T15 |
65 |
higher_val |
lower_val |
auto[1] |
46562 |
1 |
|
|
T1 |
44 |
|
T2 |
73 |
|
T11 |
49 |
higher_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T150 |
1 |
|
T151 |
2 |
|
- |
- |
higher_val |
zero_val |
auto[1] |
3 |
1 |
|
|
T153 |
1 |
|
T154 |
2 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
39876 |
1 |
|
|
T12 |
6 |
|
T13 |
1 |
|
T15 |
63 |
lower_val |
higher_val |
auto[1] |
46065 |
1 |
|
|
T1 |
41 |
|
T2 |
88 |
|
T11 |
37 |
lower_val |
lower_val |
auto[0] |
40195 |
1 |
|
|
T12 |
1 |
|
T13 |
3 |
|
T15 |
72 |
lower_val |
lower_val |
auto[1] |
45436 |
1 |
|
|
T1 |
51 |
|
T2 |
74 |
|
T11 |
37 |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T152 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
651 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T11 |
1 |
zero_val |
higher_val |
auto[1] |
259 |
1 |
|
|
T155 |
1 |
|
T156 |
3 |
|
T68 |
1 |
zero_val |
lower_val |
auto[0] |
681 |
1 |
|
|
T4 |
1 |
|
T13 |
1 |
|
T14 |
1 |
zero_val |
lower_val |
auto[1] |
232 |
1 |
|
|
T1 |
2 |
|
T155 |
1 |
|
T156 |
3 |