Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100797376	1			T1	283040		T2	158532		T11	284384
all_pins[1]	100797376	1			T1	283040		T2	158532		T11	284384
all_pins[2]	100797376	1			T1	283040		T2	158532		T11	284384

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	301530782	1			T1	848839		T2	475118		T11	852877
values[0x1]	861346	1			T1	281		T2	478		T11	275
transitions[0x0=>0x1]	859134	1			T1	281		T2	478		T11	275
transitions[0x1=>0x0]	859161	1			T1	281		T2	478		T11	275

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	100289483	1			T1	282759		T2	158054		T11	284109
all_pins[0]	values[0x1]	507893	1			T1	281		T2	478		T11	275
all_pins[0]	transitions[0x0=>0x1]	507881	1			T1	281		T2	478		T11	275
all_pins[0]	transitions[0x1=>0x0]	60	1			T49	3		T85	2		T173	3
all_pins[1]	values[0x0]	100797304	1			T1	283040		T2	158532		T11	284384
all_pins[1]	values[0x1]	72	1			T49	3		T85	2		T173	3
all_pins[1]	transitions[0x0=>0x1]	61	1			T49	3		T85	2		T173	3
all_pins[1]	transitions[0x1=>0x0]	353370	1			T22	2844		T23	1427		T29	404
all_pins[2]	values[0x0]	100443995	1			T1	283040		T2	158532		T11	284384
all_pins[2]	values[0x1]	353381	1			T22	2844		T23	1427		T29	404
all_pins[2]	transitions[0x0=>0x1]	351192	1			T22	2825		T23	1427		T29	404
all_pins[2]	transitions[0x1=>0x0]	505731	1			T1	281		T2	478		T11	275