Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	663	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5586	1			T1	26		T11	26		T12	5
len_601_800	12430	1			T1	59		T11	68		T12	6
len_401_600	8161	1			T1	55		T11	40		T12	5
len_201_400	16395	1			T1	12		T11	16		T12	2
len_65_200	73744	1			T1	10		T11	10		T12	2
len_min_for_xof_require_squeeze	995	1			T14	10		T16	9		T42	1
len_keccak_block_sizes[72]	747	1			T14	5		T16	9		T156	5
len_keccak_block_sizes[104]	755	1			T1	1		T14	5		T16	9
len_keccak_block_sizes[136]	757	1			T14	5		T16	9		T183	1
len_keccak_block_sizes[144]	282	1			T11	1		T14	5		T156	5
len_keccak_block_sizes[168]	289	1			T14	5		T23	1		T156	5
len_datapath_width	14105	1			T11	1		T12	1		T13	3
len_2_63	215134	1			T1	11		T2	310		T11	10
len_1	53	1			T1	1		T143	1		T184	1