Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	100385149	1			T2	161931		T4	15465		T14	223961
all_values[1]	100385149	1			T2	161931		T4	15465		T14	223961
all_values[2]	100385149	1			T2	161931		T4	15465		T14	223961

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

487916

1

T2

3

T4

552

T14

25

auto[1]

300667531

1

T2

485790

T4

45843

T14

671858

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

299629389

1

T2

484395

T4

45948

T14

670095

auto[1]

1526058

1

T2

1398

T4

447

T14

1788

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	157992	1			T2	1		T15	1		T17	5
all_values[0]	auto[0]	auto[1]	1997	1			T2	2		T15	2		T17	6
all_values[0]	auto[1]	auto[0]	99718471	1			T2	161464		T4	15316		T14	223365
all_values[0]	auto[1]	auto[1]	506689	1			T2	464		T4	149		T14	596
all_values[1]	auto[0]	auto[0]	163014	1			T4	275		T15	1		T18	2
all_values[1]	auto[0]	auto[1]	1421	1			T4	1		T15	2		T18	1
all_values[1]	auto[1]	auto[0]	99713449	1			T2	161465		T4	15041		T14	223365
all_values[1]	auto[1]	auto[1]	507265	1			T2	466		T4	148		T14	596
all_values[2]	auto[0]	auto[0]	161922	1			T4	275		T14	17		T16	858
all_values[2]	auto[0]	auto[1]	1570	1			T4	1		T14	8		T16	7
all_values[2]	auto[1]	auto[0]	99714541	1			T2	161465		T4	15041		T14	223348
all_values[2]	auto[1]	auto[1]	507116	1			T2	466		T4	148		T14	588