Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
347734 |
1 |
|
|
T2 |
2 |
|
T4 |
2 |
|
T14 |
780 |
auto[1] |
344956 |
1 |
|
|
T2 |
618 |
|
T4 |
308 |
|
T16 |
140 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
173658 |
1 |
|
|
T2 |
149 |
|
T4 |
78 |
|
T14 |
189 |
lower_val |
172129 |
1 |
|
|
T2 |
176 |
|
T4 |
66 |
|
T14 |
184 |
zero_val |
1726 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T14 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
346156 |
1 |
|
|
T2 |
302 |
|
T4 |
158 |
|
T14 |
402 |
lower_val |
346522 |
1 |
|
|
T2 |
318 |
|
T4 |
152 |
|
T14 |
378 |
zero_val |
12 |
1 |
|
|
T174 |
2 |
|
T175 |
2 |
|
T176 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
2 |
16 |
88.89 |
2 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
43413 |
1 |
|
|
T14 |
93 |
|
T15 |
79 |
|
T19 |
611 |
higher_val |
higher_val |
auto[1] |
43259 |
1 |
|
|
T2 |
68 |
|
T4 |
38 |
|
T16 |
23 |
higher_val |
lower_val |
auto[0] |
43657 |
1 |
|
|
T4 |
1 |
|
T14 |
96 |
|
T15 |
77 |
higher_val |
lower_val |
auto[1] |
43325 |
1 |
|
|
T2 |
81 |
|
T4 |
39 |
|
T16 |
7 |
higher_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T174 |
1 |
|
T177 |
1 |
|
- |
- |
higher_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T176 |
1 |
|
T178 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
42728 |
1 |
|
|
T14 |
87 |
|
T15 |
113 |
|
T16 |
1 |
lower_val |
higher_val |
auto[1] |
43038 |
1 |
|
|
T2 |
94 |
|
T4 |
28 |
|
T16 |
25 |
lower_val |
lower_val |
auto[0] |
43010 |
1 |
|
|
T14 |
97 |
|
T15 |
109 |
|
T19 |
574 |
lower_val |
lower_val |
auto[1] |
43350 |
1 |
|
|
T2 |
82 |
|
T4 |
38 |
|
T16 |
15 |
lower_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T175 |
1 |
|
T179 |
1 |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T178 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
663 |
1 |
|
|
T15 |
1 |
|
T16 |
1 |
|
T17 |
1 |
zero_val |
higher_val |
auto[1] |
198 |
1 |
|
|
T154 |
2 |
|
T30 |
1 |
|
T115 |
1 |
zero_val |
lower_val |
auto[0] |
635 |
1 |
|
|
T2 |
1 |
|
T4 |
1 |
|
T14 |
1 |
zero_val |
lower_val |
auto[1] |
230 |
1 |
|
|
T18 |
2 |
|
T154 |
4 |
|
T30 |
1 |