Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	100385149	1			T2	161931		T4	15465		T14	223961
all_pins[1]	100385149	1			T2	161931		T4	15465		T14	223961
all_pins[2]	100385149	1			T2	161931		T4	15465		T14	223961

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	300384482	1			T2	485329		T4	46246		T14	671287
values[0x1]	770965	1			T2	464		T4	149		T14	596
transitions[0x0=>0x1]	769341	1			T2	464		T4	149		T14	596
transitions[0x1=>0x0]	769369	1			T2	464		T4	149		T14	596

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99878460	1			T2	161467		T4	15316		T14	223365
all_pins[0]	values[0x1]	506689	1			T2	464		T4	149		T14	596
all_pins[0]	transitions[0x0=>0x1]	506676	1			T2	464		T4	149		T14	596
all_pins[0]	transitions[0x1=>0x0]	50	1			T41	3		T187	2		T188	3
all_pins[1]	values[0x0]	100385086	1			T2	161931		T4	15465		T14	223961
all_pins[1]	values[0x1]	63	1			T41	3		T187	2		T188	3
all_pins[1]	transitions[0x0=>0x1]	48	1			T41	3		T187	2		T188	3
all_pins[1]	transitions[0x1=>0x0]	264198	1			T16	184		T29	300		T31	1067
all_pins[2]	values[0x0]	100120936	1			T2	161931		T4	15465		T14	223961
all_pins[2]	values[0x1]	264213	1			T16	184		T29	300		T31	1067
all_pins[2]	transitions[0x0=>0x1]	262617	1			T16	184		T29	300		T31	1067
all_pins[2]	transitions[0x1=>0x0]	505121	1			T2	464		T4	149		T14	596