Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	654	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5411	1			T4	15		T16	4		T40	7
len_601_800	12427	1			T4	45		T16	26		T40	17
len_401_600	8337	1			T4	19		T16	16		T40	7
len_201_400	16505	1			T4	8		T16	6		T40	5
len_65_200	73650	1			T4	6		T16	1		T19	685
len_min_for_xof_require_squeeze	1013	1			T19	9		T24	1		T83	10
len_keccak_block_sizes[72]	743	1			T19	9		T147	1		T83	5
len_keccak_block_sizes[104]	753	1			T19	9		T116	2		T147	2
len_keccak_block_sizes[136]	754	1			T19	9		T147	2		T83	5
len_keccak_block_sizes[144]	273	1			T116	1		T83	5		T204	5
len_keccak_block_sizes[168]	282	1			T83	5		T204	5		T205	1
len_datapath_width	13898	1			T4	3		T17	246		T19	9
len_2_63	214294	1			T2	310		T4	58		T14	390
len_1	50	1			T116	2		T147	1		T24	1