Summary for Variable share
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
10688401 |
1 |
|
|
T2 |
3720 |
|
T4 |
18407 |
|
T14 |
2730 |
auto[1] |
25641702 |
1 |
|
|
T2 |
15500 |
|
T4 |
28050 |
|
T14 |
19500 |
Summary for Variable state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
word_access |
36211216 |
1 |
|
|
T2 |
19220 |
|
T4 |
46394 |
|
T14 |
22230 |
triple_byte_access |
39449 |
1 |
|
|
T4 |
30 |
|
T16 |
17 |
|
T19 |
279 |
halfword_access |
39830 |
1 |
|
|
T4 |
13 |
|
T16 |
19 |
|
T19 |
279 |
byte_access |
39608 |
1 |
|
|
T4 |
20 |
|
T16 |
12 |
|
T19 |
279 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
[auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
word_access |
10569514 |
1 |
|
|
T2 |
3720 |
|
T4 |
18344 |
|
T14 |
2730 |
auto[0] |
triple_byte_access |
39449 |
1 |
|
|
T4 |
30 |
|
T16 |
17 |
|
T19 |
279 |
auto[0] |
halfword_access |
39830 |
1 |
|
|
T4 |
13 |
|
T16 |
19 |
|
T19 |
279 |
auto[0] |
byte_access |
39608 |
1 |
|
|
T4 |
20 |
|
T16 |
12 |
|
T19 |
279 |
auto[1] |
word_access |
25641702 |
1 |
|
|
T2 |
15500 |
|
T4 |
28050 |
|
T14 |
19500 |