Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	99566254	1			T1	212034		T2	159548		T3	558917
all_values[1]	99566254	1			T1	212034		T2	159548		T3	558917
all_values[2]	99566254	1			T1	212034		T2	159548		T3	558917

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

463776

1

T1

3

T2

7

T13

84

auto[1]

298234986

1

T1

636099

T2

478637

T3

167675

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

297168870

1

T1

634407

T2

477279

T3

166622

auto[1]

1529892

1

T1

1695

T2

1365

T3

10524

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	142087	1			T2	3		T13	24		T4	7
all_values[0]	auto[0]	auto[1]	1975	1			T2	4		T13	4		T15	4
all_values[0]	auto[1]	auto[0]	98914203	1			T1	211469		T2	159090		T3	555409
all_values[0]	auto[1]	auto[1]	507989	1			T1	565		T2	451		T3	3508
all_values[1]	auto[0]	auto[0]	165503	1			T1	2		T13	10		T15	43
all_values[1]	auto[0]	auto[1]	1410	1			T1	1		T13	2		T15	2
all_values[1]	auto[1]	auto[0]	98890787	1			T1	211467		T2	159093		T3	555409
all_values[1]	auto[1]	auto[1]	508554	1			T1	564		T2	455		T3	3508
all_values[2]	auto[0]	auto[0]	151139	1			T13	39		T4	7		T15	578
all_values[2]	auto[0]	auto[1]	1662	1			T13	5		T15	7		T17	1
all_values[2]	auto[1]	auto[0]	98905151	1			T1	211469		T2	159093		T3	555409
all_values[2]	auto[1]	auto[1]	508302	1			T1	565		T2	455		T3	3508