Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	99566254	1			T1	212034		T2	159548		T3	558917
all_pins[1]	99566254	1			T1	212034		T2	159548		T3	558917
all_pins[2]	99566254	1			T1	212034		T2	159548		T3	558917

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	297908020	1			T1	635537		T2	478193		T3	167324
values[0x1]	790742	1			T1	565		T2	451		T3	3508
transitions[0x0=>0x1]	788996	1			T1	565		T2	451		T3	3508
transitions[0x1=>0x0]	789022	1			T1	565		T2	451		T3	3508

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	99058265	1			T1	211469		T2	159097		T3	555409
all_pins[0]	values[0x1]	507989	1			T1	565		T2	451		T3	3508
all_pins[0]	transitions[0x0=>0x1]	507972	1			T1	565		T2	451		T3	3508
all_pins[0]	transitions[0x1=>0x0]	85	1			T44	3		T45	3		T175	7
all_pins[1]	values[0x0]	99566152	1			T1	212034		T2	159548		T3	558917
all_pins[1]	values[0x1]	102	1			T44	3		T45	3		T175	7
all_pins[1]	transitions[0x0=>0x1]	80	1			T44	3		T45	3		T175	7
all_pins[1]	transitions[0x1=>0x0]	282629	1			T28	102		T24	3021		T29	703
all_pins[2]	values[0x0]	99283603	1			T1	212034		T2	159548		T3	558917
all_pins[2]	values[0x1]	282651	1			T28	102		T24	3021		T29	703
all_pins[2]	transitions[0x0=>0x1]	280944	1			T28	102		T24	3002		T29	703
all_pins[2]	transitions[0x1=>0x0]	506308	1			T1	565		T2	451		T3	3508