Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	65110516	1			T1	376		T2	270		T3	2589
all_values[1]	65110516	1			T1	376		T2	270		T3	2589
all_values[2]	65110516	1			T1	376		T2	270		T3	2589

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

506924

1

T1

325

T2

6

T13

7

auto[1]

194824624

1

T1

803

T2

804

T3

7767

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

194450754

1

T1

1125

T2

765

T3

7680

auto[1]

880794

1

T1

3

T2

45

T3

87

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	184904	1			T1	1		T13	5		T16	1
all_values[0]	auto[0]	auto[1]	2008	1			T13	2		T16	2		T17	2
all_values[0]	auto[1]	auto[0]	64632014	1			T1	374		T2	255		T3	2560
all_values[0]	auto[1]	auto[1]	291590	1			T1	1		T2	15		T3	29
all_values[1]	auto[0]	auto[0]	162337	1			T1	323		T2	5		T16	11
all_values[1]	auto[0]	auto[1]	1532	1			T1	1		T2	1		T16	6
all_values[1]	auto[1]	auto[0]	64654581	1			T1	52		T2	250		T3	2560
all_values[1]	auto[1]	auto[1]	292066	1			T2	14		T3	29		T12	458
all_values[2]	auto[0]	auto[0]	154699	1			T14	297		T18	17		T86	10
all_values[2]	auto[0]	auto[1]	1444	1			T14	1		T18	1		T86	6
all_values[2]	auto[1]	auto[0]	64662219	1			T1	375		T2	255		T3	2560
all_values[2]	auto[1]	auto[1]	292154	1			T1	1		T2	15		T3	29