Summary for Variable entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 198558 | 1 |  |  | T1 | 8 |  | T2 | 2 |  | T3 | 36 | 
| auto[1] | 206856 | 1 |  |  | T2 | 16 |  | T13 | 16 |  | T14 | 30 | 
Summary for Variable prescaler_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 3 | 0 | 3 | 100.00 | 
User Defined Bins for prescaler_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 101549 | 1 |  |  | T1 | 1 |  | T2 | 3 |  | T3 | 16 | 
| lower_val | 100465 | 1 |  |  | T1 | 4 |  | T2 | 6 |  | T3 | 3 | 
| zero_val | 1494 | 1 |  |  | T1 | 1 |  | T2 | 1 |  | T3 | 1 | 
Summary for Variable wait_timer_val
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 3 | 0 | 3 | 100.00 | 
User Defined Bins for wait_timer_val
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | 202816 | 1 |  |  | T1 | 4 |  | T2 | 8 |  | T3 | 18 | 
| lower_val | 202596 | 1 |  |  | T1 | 4 |  | T2 | 10 |  | T3 | 18 | 
| zero_val | 2 | 1 |  |  | T146 | 2 |  | - | - |  | - | - | 
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| Automatically Generated Cross Bins | 18 | 6 | 12 | 66.67 | 6 | 
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS | 
| * | [zero_val] | * | -- | -- | 6 |  | 
Covered bins
| prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| higher_val | higher_val | auto[0] | 24600 | 1 |  |  | T1 | 1 |  | T3 | 8 |  | T12 | 75 | 
| higher_val | higher_val | auto[1] | 26108 | 1 |  |  | T2 | 2 |  | T14 | 1 |  | T15 | 104 | 
| higher_val | lower_val | auto[0] | 25050 | 1 |  |  | T3 | 8 |  | T12 | 75 |  | T5 | 1 | 
| higher_val | lower_val | auto[1] | 25791 | 1 |  |  | T2 | 1 |  | T13 | 2 |  | T14 | 1 | 
| lower_val | higher_val | auto[0] | 24654 | 1 |  |  | T1 | 2 |  | T3 | 1 |  | T12 | 59 | 
| lower_val | higher_val | auto[1] | 25720 | 1 |  |  | T2 | 2 |  | T13 | 3 |  | T14 | 6 | 
| lower_val | lower_val | auto[0] | 24789 | 1 |  |  | T1 | 2 |  | T2 | 1 |  | T3 | 2 | 
| lower_val | lower_val | auto[1] | 25302 | 1 |  |  | T2 | 3 |  | T13 | 3 |  | T14 | 6 | 
| zero_val | higher_val | auto[0] | 594 | 1 |  |  | T12 | 3 |  | T14 | 1 |  | T16 | 1 | 
| zero_val | higher_val | auto[1] | 162 | 1 |  |  | T15 | 4 |  | T147 | 3 |  | T23 | 1 | 
| zero_val | lower_val | auto[0] | 548 | 1 |  |  | T1 | 1 |  | T2 | 1 |  | T3 | 1 | 
| zero_val | lower_val | auto[1] | 190 | 1 |  |  | T147 | 3 |  | T23 | 3 |  | T89 | 2 |