Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

---

Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	5978	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	6465	1			T12	24		T15	17		T16	17
len_5001_7500	11345	1			T12	24		T15	17		T16	17
len_2501_5000	6945	1			T12	24		T15	17		T16	17
len_1025_2500	4124	1			T12	14		T15	10		T16	10
len_769_1024	6077	1			T1	1		T3	5		T12	2
len_513_768	6597	1			T3	5		T12	3		T14	3
len_257_512	12267	1			T3	3		T12	2		T14	3
len_0_256	135680	1			T2	9		T3	5		T12	211
len_keccak_block_sizes[72]	528	1			T12	2		T15	2		T16	2
len_keccak_block_sizes[104]	430	1			T12	2		T15	2		T16	2
len_keccak_block_sizes[136]	338	1			T15	2		T16	2		T86	2
len_keccak_block_sizes[144]	237	1			T15	2		T16	2		T86	2
len_keccak_block_sizes[168]	131	1			T147	3		T38	1		T168	3
len_1	569	1			T12	2		T15	2		T16	2
len_0	987	1			T12	2		T15	2		T16	2