Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	65110516	1			T1	376		T2	270		T3	2589
all_pins[1]	65110516	1			T1	376		T2	270		T3	2589
all_pins[2]	65110516	1			T1	376		T2	270		T3	2589

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	194748916	1			T1	1127		T2	795		T3	7729
values[0x1]	582632	1			T1	1		T2	15		T3	38
transitions[0x0=>0x1]	580813	1			T1	1		T2	15		T3	38
transitions[0x1=>0x0]	580843	1			T1	1		T2	15		T3	38

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	64818926	1			T1	375		T2	255		T3	2560
all_pins[0]	values[0x1]	291590	1			T1	1		T2	15		T3	29
all_pins[0]	transitions[0x0=>0x1]	291582	1			T1	1		T2	15		T3	29
all_pins[0]	transitions[0x1=>0x0]	51	1			T18	3		T157	3		T158	4
all_pins[1]	values[0x0]	65110457	1			T1	376		T2	270		T3	2589
all_pins[1]	values[0x1]	59	1			T18	3		T157	3		T158	4
all_pins[1]	transitions[0x0=>0x1]	48	1			T18	3		T157	3		T158	4
all_pins[1]	transitions[0x1=>0x0]	290972	1			T3	9		T14	1489		T28	1112
all_pins[2]	values[0x0]	64819533	1			T1	376		T2	270		T3	2580
all_pins[2]	values[0x1]	290983	1			T3	9		T14	1489		T28	1112
all_pins[2]	transitions[0x0=>0x1]	289183	1			T3	9		T14	1480		T28	1112
all_pins[2]	transitions[0x1=>0x0]	289820	1			T1	1		T2	15		T3	29