Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	616	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5245	1			T3	2		T14	3		T17	3
len_601_800	12079	1			T3	4		T14	1		T17	21
len_401_600	8037	1			T1	1		T3	5		T17	18
len_201_400	8290	1			T3	4		T14	4		T17	3
len_65_200	31254	1			T17	3		T18	4		T80	8
len_min_for_xof_require_squeeze	411	1			T28	1		T147	10		T168	9
len_keccak_block_sizes[72]	321	1			T26	1		T147	5		T52	1
len_keccak_block_sizes[104]	308	1			T147	5		T171	1		T168	9
len_keccak_block_sizes[136]	306	1			T147	5		T168	9		T72	9
len_keccak_block_sizes[144]	115	1			T147	5		T172	1		T173	1
len_keccak_block_sizes[168]	118	1			T129	1		T147	5		T171	1
len_datapath_width	13648	1			T2	3		T13	3		T79	246
len_2_63	122276	1			T1	2		T2	6		T3	1
len_1	52	1			T124	1		T171	3		T71	1