Summary for Variable in_app_keymgr
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for in_app_keymgr
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 200997 | 1 |  |  | T1 | 4 |  | T2 | 9 |  | T3 | 18 | 
| auto[1] | 3462 | 1 |  |  | T1 | 2 |  | T4 | 1 |  | T5 | 1 | 
Summary for Variable kmac_mode
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for kmac_mode
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 167914 | 1 |  |  | T3 | 2 |  | T12 | 298 |  | T14 | 16 | 
| auto[1] | 36545 | 1 |  |  | T1 | 6 |  | T2 | 9 |  | T3 | 16 | 
Summary for Variable sideload
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Automatically Generated Bins | 2 | 0 | 2 | 100.00 | 
Automatically Generated Bins for sideload
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| auto[0] | 190355 | 1 |  |  | T1 | 4 |  | T2 | 9 |  | T3 | 14 | 
| auto[1] | 14104 | 1 |  |  | T1 | 2 |  | T3 | 4 |  | T4 | 1 | 
Summary for Cross sideload_cross
Samples crossed: sideload kmac_mode in_app_keymgr
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING | 
| User Defined Cross Bins | 4 | 0 | 4 | 100.00 |  | 
User Defined Cross Bins for sideload_cross
Bins
| NAME | COUNT | AT LEAST | STATUS |  | TEST | COUNT |  | TEST | COUNT |  | TEST | COUNT | 
| sw_kmac_valid_sideload | 14104 | 1 |  |  | T1 | 2 |  | T3 | 4 |  | T4 | 1 | 
| sw_kmac_invalid_sideload | 190355 | 1 |  |  | T1 | 4 |  | T2 | 9 |  | T3 | 14 | 
| app_valid_sideload | 14104 | 1 |  |  | T1 | 2 |  | T3 | 4 |  | T4 | 1 | 
| app_invalid_sideload | 190355 | 1 |  |  | T1 | 4 |  | T2 | 9 |  | T3 | 14 |