Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	62778493	1			T1	289		T2	33		T3	23631
all_values[1]	62778493	1			T1	289		T2	33		T3	23631
all_values[2]	62778493	1			T1	289		T2	33		T3	23631

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

476210

1

T1

75

T2

3

T13

11

auto[1]

187859269

1

T1

792

T2

96

T3

70893

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

187499799

1

T1

831

T2

99

T3

70221

auto[1]

835680

1

T1

36

T3

672

T13

1650

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	145189	1			T13	5		T14	218		T15	12
all_values[0]	auto[0]	auto[1]	1781	1			T13	6		T14	2		T15	10
all_values[0]	auto[1]	auto[0]	62354744	1			T1	277		T2	33		T3	23407
all_values[0]	auto[1]	auto[1]	276779	1			T1	12		T3	224		T13	544
all_values[1]	auto[0]	auto[0]	176917	1			T18	232		T77	170		T28	115
all_values[1]	auto[0]	auto[1]	1437	1			T18	1		T77	2		T28	1
all_values[1]	auto[1]	auto[0]	62323016	1			T1	277		T2	33		T3	23407
all_values[1]	auto[1]	auto[1]	277123	1			T1	12		T3	224		T13	550
all_values[2]	auto[0]	auto[0]	149522	1			T1	70		T2	3		T15	1
all_values[2]	auto[0]	auto[1]	1364	1			T1	5		T15	2		T17	4
all_values[2]	auto[1]	auto[0]	62350411	1			T1	207		T2	30		T3	23407
all_values[2]	auto[1]	auto[1]	277196	1			T1	7		T3	224		T13	550