Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
180096 |
1 |
|
|
T1 |
18 |
|
T2 |
64 |
|
T3 |
2 |
auto[1] |
205850 |
1 |
|
|
T3 |
332 |
|
T14 |
110 |
|
T16 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
96644 |
1 |
|
|
T1 |
6 |
|
T2 |
14 |
|
T3 |
76 |
lower_val |
95429 |
1 |
|
|
T1 |
5 |
|
T2 |
8 |
|
T3 |
67 |
zero_val |
1432 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
192524 |
1 |
|
|
T1 |
8 |
|
T2 |
30 |
|
T3 |
176 |
lower_val |
193412 |
1 |
|
|
T1 |
10 |
|
T2 |
34 |
|
T3 |
158 |
zero_val |
10 |
1 |
|
|
T137 |
2 |
|
T138 |
2 |
|
T139 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
22699 |
1 |
|
|
T1 |
5 |
|
T2 |
6 |
|
T13 |
106 |
higher_val |
higher_val |
auto[1] |
25668 |
1 |
|
|
T3 |
40 |
|
T14 |
12 |
|
T16 |
2 |
higher_val |
lower_val |
auto[0] |
22542 |
1 |
|
|
T1 |
1 |
|
T2 |
8 |
|
T13 |
102 |
higher_val |
lower_val |
auto[1] |
25735 |
1 |
|
|
T3 |
36 |
|
T14 |
14 |
|
T17 |
1 |
lower_val |
higher_val |
auto[0] |
21961 |
1 |
|
|
T1 |
1 |
|
T2 |
5 |
|
T13 |
98 |
lower_val |
higher_val |
auto[1] |
25565 |
1 |
|
|
T3 |
39 |
|
T14 |
15 |
|
T16 |
7 |
lower_val |
lower_val |
auto[0] |
22229 |
1 |
|
|
T1 |
4 |
|
T2 |
3 |
|
T13 |
102 |
lower_val |
lower_val |
auto[1] |
25668 |
1 |
|
|
T3 |
28 |
|
T14 |
17 |
|
T17 |
2 |
lower_val |
zero_val |
auto[0] |
3 |
1 |
|
|
T137 |
2 |
|
T139 |
1 |
|
- |
- |
lower_val |
zero_val |
auto[1] |
3 |
1 |
|
|
T138 |
1 |
|
T140 |
1 |
|
T141 |
1 |
zero_val |
higher_val |
auto[0] |
547 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T13 |
1 |
zero_val |
higher_val |
auto[1] |
169 |
1 |
|
|
T24 |
3 |
|
T86 |
1 |
|
T25 |
1 |
zero_val |
lower_val |
auto[0] |
535 |
1 |
|
|
T3 |
1 |
|
T13 |
2 |
|
T14 |
1 |
zero_val |
lower_val |
auto[1] |
181 |
1 |
|
|
T24 |
2 |
|
T86 |
1 |
|
T27 |
2 |