Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	62778493	1			T1	289		T2	33		T3	23631
all_pins[1]	62778493	1			T1	289		T2	33		T3	23631
all_pins[2]	62778493	1			T1	289		T2	33		T3	23631

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	187749496	1			T1	855		T2	99		T3	69250
values[0x1]	585983	1			T1	12		T3	1643		T13	544
transitions[0x0=>0x1]	584112	1			T1	12		T3	1643		T13	544
transitions[0x1=>0x0]	584138	1			T1	12		T3	1643		T13	544

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	62501714	1			T1	277		T2	33		T3	23407
all_pins[0]	values[0x1]	276779	1			T1	12		T3	224		T13	544
all_pins[0]	transitions[0x0=>0x1]	276767	1			T1	12		T3	224		T13	544
all_pins[0]	transitions[0x1=>0x0]	45	1			T154	3		T155	3		T156	2
all_pins[1]	values[0x0]	62778436	1			T1	289		T2	33		T3	23631
all_pins[1]	values[0x1]	57	1			T154	3		T155	3		T156	2
all_pins[1]	transitions[0x0=>0x1]	43	1			T154	3		T155	3		T156	2
all_pins[1]	transitions[0x1=>0x0]	309133	1			T3	1419		T14	18		T18	873
all_pins[2]	values[0x0]	62469346	1			T1	289		T2	33		T3	22212
all_pins[2]	values[0x1]	309147	1			T3	1419		T14	18		T18	873
all_pins[2]	transitions[0x0=>0x1]	307302	1			T3	1419		T14	18		T18	872
all_pins[2]	transitions[0x1=>0x0]	274960	1			T1	12		T3	224		T13	544