Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	68786776	1			T1	3671		T2	7954		T3	163262
all_values[1]	68786776	1			T1	3671		T2	7954		T3	163262
all_values[2]	68786776	1			T1	3671		T2	7954		T3	163262

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

510046

1

T2

838

T3

14

T14

20

auto[1]

205850282

1

T1

11013

T2

23024

T3

489772

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

205411584

1

T1

10902

T2

23631

T3

488349

auto[1]

948744

1

T1

111

T2

231

T3

1437

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	162668	1			T2	832		T3	3		T28	83
all_values[0]	auto[0]	auto[1]	2069	1			T2	6		T3	4		T28	6
all_values[0]	auto[1]	auto[0]	68307860	1			T1	3634		T2	7045		T3	162780
all_values[0]	auto[1]	auto[1]	314179	1			T1	37		T2	71		T3	475
all_values[1]	auto[0]	auto[0]	154778	1			T3	3		T14	6		T16	402
all_values[1]	auto[0]	auto[1]	1494	1			T3	4		T14	1		T16	2
all_values[1]	auto[1]	auto[0]	68315750	1			T1	3634		T2	7877		T3	162780
all_values[1]	auto[1]	auto[1]	314754	1			T1	37		T2	77		T3	475
all_values[2]	auto[0]	auto[0]	187559	1			T14	11		T15	605		T16	402
all_values[2]	auto[0]	auto[1]	1478	1			T14	2		T15	4		T16	2
all_values[2]	auto[1]	auto[0]	68282969	1			T1	3634		T2	7877		T3	162783
all_values[2]	auto[1]	auto[1]	314770	1			T1	37		T2	77		T3	479