Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
205132 |
1 |
|
|
T1 |
76 |
|
T2 |
112 |
|
T3 |
620 |
auto[1] |
230738 |
1 |
|
|
T17 |
746 |
|
T52 |
618 |
|
T28 |
326 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
109522 |
1 |
|
|
T1 |
14 |
|
T2 |
24 |
|
T3 |
148 |
lower_val |
107357 |
1 |
|
|
T1 |
15 |
|
T2 |
30 |
|
T3 |
153 |
zero_val |
1518 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
217260 |
1 |
|
|
T1 |
28 |
|
T2 |
54 |
|
T3 |
288 |
lower_val |
218606 |
1 |
|
|
T1 |
48 |
|
T2 |
58 |
|
T3 |
332 |
zero_val |
4 |
1 |
|
|
T150 |
2 |
|
T151 |
2 |
|
- |
- |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
4 |
14 |
77.78 |
4 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val , lower_val] |
[zero_val] |
[auto[0]] |
-- |
-- |
2 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
25917 |
1 |
|
|
T1 |
5 |
|
T2 |
10 |
|
T3 |
67 |
higher_val |
higher_val |
auto[1] |
28856 |
1 |
|
|
T17 |
88 |
|
T52 |
82 |
|
T28 |
50 |
higher_val |
lower_val |
auto[0] |
25840 |
1 |
|
|
T1 |
9 |
|
T2 |
14 |
|
T3 |
81 |
higher_val |
lower_val |
auto[1] |
28908 |
1 |
|
|
T17 |
95 |
|
T52 |
80 |
|
T28 |
23 |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T150 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
24988 |
1 |
|
|
T1 |
5 |
|
T2 |
12 |
|
T3 |
81 |
lower_val |
higher_val |
auto[1] |
28344 |
1 |
|
|
T17 |
99 |
|
T52 |
51 |
|
T28 |
52 |
lower_val |
lower_val |
auto[0] |
25294 |
1 |
|
|
T1 |
10 |
|
T2 |
18 |
|
T3 |
72 |
lower_val |
lower_val |
auto[1] |
28730 |
1 |
|
|
T17 |
81 |
|
T52 |
87 |
|
T28 |
45 |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T150 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
572 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
higher_val |
auto[1] |
186 |
1 |
|
|
T52 |
1 |
|
T139 |
1 |
|
T45 |
4 |
zero_val |
lower_val |
auto[0] |
570 |
1 |
|
|
T3 |
2 |
|
T14 |
1 |
|
T16 |
1 |
zero_val |
lower_val |
auto[1] |
190 |
1 |
|
|
T52 |
1 |
|
T139 |
1 |
|
T45 |
5 |