Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::msg_len_cg

Group : kmac_env_pkg::kmac_env_cov::msg_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::msg_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
msg_len	15	0	15	100.00	100	1	1	0

Summary for Variable msg_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	15	0	15	100.00

User Defined Bins for msg_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	6453	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_7501_10000	6847	1			T3	24		T17	19		T52	24
len_5001_7500	11800	1			T3	24		T17	18		T52	24
len_2501_5000	7267	1			T3	24		T17	18		T52	24
len_1025_2500	4276	1			T3	14		T17	11		T52	14
len_769_1024	5811	1			T1	7		T2	12		T3	2
len_513_768	6103	1			T1	5		T2	10		T3	3
len_257_512	12831	1			T1	4		T2	13		T3	2
len_0_256	149265	1			T1	6		T2	15		T3	211
len_keccak_block_sizes[72]	554	1			T3	2		T17	2		T52	2
len_keccak_block_sizes[104]	457	1			T3	2		T17	2		T52	2
len_keccak_block_sizes[136]	358	1			T17	2		T92	2		T130	3
len_keccak_block_sizes[144]	258	1			T130	3		T79	2		T139	3
len_keccak_block_sizes[168]	160	1			T130	3		T139	3		T44	1
len_1	589	1			T3	2		T17	2		T52	2
len_0	982	1			T3	2		T17	2		T52	2