Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	68786776	1			T1	3671		T2	7954		T3	163262
all_pins[1]	68786776	1			T1	3671		T2	7954		T3	163262
all_pins[2]	68786776	1			T1	3671		T2	7954		T3	163262

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	205766584	1			T1	10976		T2	23177		T3	489311
values[0x1]	593744	1			T1	37		T2	685		T3	475
transitions[0x0=>0x1]	592023	1			T1	37		T2	685		T3	475
transitions[0x1=>0x0]	592052	1			T1	37		T2	685		T3	475

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	68472597	1			T1	3634		T2	7883		T3	162787
all_pins[0]	values[0x1]	314179	1			T1	37		T2	71		T3	475
all_pins[0]	transitions[0x0=>0x1]	314163	1			T1	37		T2	71		T3	475
all_pins[0]	transitions[0x1=>0x0]	77	1			T165	2		T166	9		T41	4
all_pins[1]	values[0x0]	68786683	1			T1	3671		T2	7954		T3	163262
all_pins[1]	values[0x1]	93	1			T165	2		T166	9		T41	4
all_pins[1]	transitions[0x0=>0x1]	82	1			T165	2		T166	9		T41	4
all_pins[1]	transitions[0x1=>0x0]	279461	1			T2	614		T22	5769		T23	758
all_pins[2]	values[0x0]	68507304	1			T1	3671		T2	7340		T3	163262
all_pins[2]	values[0x1]	279472	1			T2	614		T22	5769		T23	758
all_pins[2]	transitions[0x0=>0x1]	277778	1			T2	614		T22	5732		T23	753
all_pins[2]	transitions[0x1=>0x0]	312514	1			T1	37		T2	71		T3	475