Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	565	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5159	1			T1	4		T2	8		T15	4
len_601_800	11682	1			T1	7		T2	12		T15	4
len_401_600	7816	1			T1	6		T2	7		T15	3
len_201_400	9405	1			T1	3		T2	3		T15	1
len_65_200	35998	1			T1	1		T2	3		T15	1
len_min_for_xof_require_squeeze	482	1			T130	10		T139	9		T87	1
len_keccak_block_sizes[72]	372	1			T130	5		T139	9		T45	2
len_keccak_block_sizes[104]	356	1			T28	2		T80	1		T130	5
len_keccak_block_sizes[136]	361	1			T16	1		T130	5		T139	9
len_keccak_block_sizes[144]	143	1			T130	5		T112	1		T176	5
len_keccak_block_sizes[168]	150	1			T130	5		T86	1		T177	1
len_datapath_width	13694	1			T2	1		T14	3		T28	15
len_2_63	132543	1			T1	17		T2	8		T3	310
len_1	54	1			T45	2		T86	2		T87	1