Summary for Variable share
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for share
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
8292087 |
1 |
|
|
T1 |
4077 |
|
T2 |
7489 |
|
T3 |
3720 |
| auto[1] |
18051827 |
1 |
|
|
T1 |
6438 |
|
T2 |
11224 |
|
T3 |
15500 |
Summary for Variable state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
| User Defined Bins |
4 |
0 |
4 |
100.00 |
User Defined Bins for state_read_mask
Bins
| NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| word_access |
26275300 |
1 |
|
|
T1 |
10498 |
|
T2 |
18682 |
|
T3 |
19220 |
| triple_byte_access |
22829 |
1 |
|
|
T1 |
4 |
|
T2 |
10 |
|
T15 |
1 |
| halfword_access |
22978 |
1 |
|
|
T1 |
8 |
|
T2 |
12 |
|
T15 |
3 |
| byte_access |
22807 |
1 |
|
|
T1 |
5 |
|
T2 |
9 |
|
T15 |
4 |
Summary for Cross state_mask_share_cross
Samples crossed: share state_read_mask
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
| Automatically Generated Cross Bins |
8 |
3 |
5 |
62.50 |
3 |
Automatically Generated Cross Bins for state_mask_share_cross
Uncovered bins
| share | state_read_mask | COUNT | AT LEAST | NUMBER | STATUS |
| [auto[1]] |
[triple_byte_access , halfword_access , byte_access] |
-- |
-- |
3 |
|
Covered bins
| share | state_read_mask | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
| auto[0] |
word_access |
8223473 |
1 |
|
|
T1 |
4060 |
|
T2 |
7458 |
|
T3 |
3720 |
| auto[0] |
triple_byte_access |
22829 |
1 |
|
|
T1 |
4 |
|
T2 |
10 |
|
T15 |
1 |
| auto[0] |
halfword_access |
22978 |
1 |
|
|
T1 |
8 |
|
T2 |
12 |
|
T15 |
3 |
| auto[0] |
byte_access |
22807 |
1 |
|
|
T1 |
5 |
|
T2 |
9 |
|
T15 |
4 |
| auto[1] |
word_access |
18051827 |
1 |
|
|
T1 |
6438 |
|
T2 |
11224 |
|
T3 |
15500 |