Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	69242066	1			T1	161748		T2	450873		T3	431
all_values[1]	69242066	1			T1	161748		T2	450873		T3	431
all_values[2]	69242066	1			T1	161748		T2	450873		T3	431

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

432628

1

T1

24

T3

32

T13

3

auto[1]

207293570

1

T1

485220

T2

135261

T3

1261

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

206794554

1

T1

483840

T2

134240

T3

1098

auto[1]

931644

1

T1

1404

T2

10218

T3

195

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	150312	1			T3	10		T13	1		T15	6074
all_values[0]	auto[0]	auto[1]	1946	1			T3	2		T13	2		T15	16
all_values[0]	auto[1]	auto[0]	68781206	1			T1	161280		T2	447467		T3	356
all_values[0]	auto[1]	auto[1]	308602	1			T1	468		T2	3406		T3	63
all_values[1]	auto[0]	auto[0]	129751	1			T1	2		T3	17		T15	47
all_values[1]	auto[0]	auto[1]	1463	1			T1	1		T3	3		T15	4
all_values[1]	auto[1]	auto[0]	68801767	1			T1	161278		T2	447467		T3	349
all_values[1]	auto[1]	auto[1]	309085	1			T1	467		T2	3406		T3	62
all_values[2]	auto[0]	auto[0]	147615	1			T1	14		T15	5662		T16	4
all_values[2]	auto[0]	auto[1]	1541	1			T1	7		T15	11		T16	2
all_values[2]	auto[1]	auto[0]	68783903	1			T1	161266		T2	447467		T3	366
all_values[2]	auto[1]	auto[1]	309007	1			T1	461		T2	3406		T3	65