Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
225626 |
1 |
|
|
T1 |
620 |
|
T2 |
2 |
|
T3 |
80 |
auto[1] |
201958 |
1 |
|
|
T2 |
4528 |
|
T14 |
360 |
|
T15 |
336 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
107464 |
1 |
|
|
T1 |
166 |
|
T2 |
1181 |
|
T3 |
21 |
lower_val |
106019 |
1 |
|
|
T1 |
158 |
|
T2 |
1156 |
|
T3 |
16 |
zero_val |
1510 |
1 |
|
|
T1 |
1 |
|
T2 |
13 |
|
T3 |
1 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
214068 |
1 |
|
|
T1 |
314 |
|
T2 |
2272 |
|
T3 |
28 |
lower_val |
213508 |
1 |
|
|
T1 |
306 |
|
T2 |
2258 |
|
T3 |
52 |
zero_val |
8 |
1 |
|
|
T87 |
2 |
|
T160 |
2 |
|
T161 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[lower_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
28470 |
1 |
|
|
T1 |
75 |
|
T3 |
8 |
|
T13 |
76 |
higher_val |
higher_val |
auto[1] |
25478 |
1 |
|
|
T2 |
582 |
|
T14 |
42 |
|
T15 |
51 |
higher_val |
lower_val |
auto[0] |
28339 |
1 |
|
|
T1 |
91 |
|
T3 |
13 |
|
T13 |
91 |
higher_val |
lower_val |
auto[1] |
25173 |
1 |
|
|
T2 |
599 |
|
T14 |
43 |
|
T15 |
51 |
higher_val |
zero_val |
auto[0] |
2 |
1 |
|
|
T160 |
2 |
|
- |
- |
|
- |
- |
higher_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T87 |
1 |
|
T162 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
27586 |
1 |
|
|
T1 |
80 |
|
T2 |
1 |
|
T3 |
4 |
lower_val |
higher_val |
auto[1] |
25249 |
1 |
|
|
T2 |
578 |
|
T14 |
37 |
|
T15 |
35 |
lower_val |
lower_val |
auto[0] |
27954 |
1 |
|
|
T1 |
78 |
|
T3 |
12 |
|
T13 |
92 |
lower_val |
lower_val |
auto[1] |
25228 |
1 |
|
|
T2 |
577 |
|
T14 |
45 |
|
T15 |
56 |
lower_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T161 |
2 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
569 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T3 |
1 |
zero_val |
higher_val |
auto[1] |
167 |
1 |
|
|
T2 |
6 |
|
T15 |
2 |
|
T18 |
1 |
zero_val |
lower_val |
auto[0] |
603 |
1 |
|
|
T13 |
2 |
|
T14 |
1 |
|
T15 |
3 |
zero_val |
lower_val |
auto[1] |
171 |
1 |
|
|
T2 |
6 |
|
T15 |
1 |
|
T18 |
1 |