Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	69242066	1			T1	161748		T2	450873		T3	431
all_pins[1]	69242066	1			T1	161748		T2	450873		T3	431
all_pins[2]	69242066	1			T1	161748		T2	450873		T3	431

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	207144193	1			T1	484776		T2	134921		T3	1230
values[0x1]	582005	1			T1	468		T2	3406		T3	63
transitions[0x0=>0x1]	580331	1			T1	468		T2	3406		T3	63
transitions[0x1=>0x0]	580357	1			T1	468		T2	3406		T3	63

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	68933464	1			T1	161280		T2	447467		T3	368
all_pins[0]	values[0x1]	308602	1			T1	468		T2	3406		T3	63
all_pins[0]	transitions[0x0=>0x1]	308587	1			T1	468		T2	3406		T3	63
all_pins[0]	transitions[0x1=>0x0]	54	1			T25	4		T174	2		T175	3
all_pins[1]	values[0x0]	69241997	1			T1	161748		T2	450873		T3	431
all_pins[1]	values[0x1]	69	1			T25	4		T174	2		T175	3
all_pins[1]	transitions[0x0=>0x1]	64	1			T25	4		T174	2		T175	3
all_pins[1]	transitions[0x1=>0x0]	273329	1			T15	6504		T23	838		T24	1854
all_pins[2]	values[0x0]	68968732	1			T1	161748		T2	450873		T3	431
all_pins[2]	values[0x1]	273334	1			T15	6504		T23	838		T24	1854
all_pins[2]	transitions[0x0=>0x1]	271680	1			T15	6461		T23	838		T24	1838
all_pins[2]	transitions[0x1=>0x0]	306974	1			T1	468		T2	3406		T3	63