Unified Coverage Report :: Group :: kmac_env_pkg::kmac_env_cov::output_digest_len_cg

Group : kmac_env_pkg::kmac_env_cov::output_digest_len_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_kmac_env_0.1/kmac_env_cov.sv

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Summary for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00

Variables for Group kmac_env_pkg::kmac_env_cov::output_digest_len_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
output_digest_len	14	0	14	100.00	100	1	1	0

Summary for Variable output_digest_len

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	14	0	14	100.00

User Defined Bins for output_digest_len

Excluded/Illegal bins

NAME	COUNT	STATUS
remainder	578	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
len_801_1000	5158	1			T14	25		T15	37		T23	10
len_601_800	11783	1			T14	71		T15	100		T23	28
len_401_600	7830	1			T14	46		T15	59		T23	17
len_201_400	9437	1			T2	251		T14	18		T15	20
len_65_200	34753	1			T2	680		T3	22		T14	12
len_min_for_xof_require_squeeze	472	1			T2	10		T15	1		T18	10
len_keccak_block_sizes[72]	343	1			T2	5		T18	5		T19	1
len_keccak_block_sizes[104]	346	1			T2	5		T18	5		T87	5
len_keccak_block_sizes[136]	338	1			T2	5		T18	5		T19	2
len_keccak_block_sizes[144]	141	1			T2	5		T14	3		T18	5
len_keccak_block_sizes[168]	151	1			T2	5		T3	1		T15	2
len_datapath_width	13704	1			T2	5		T3	1		T15	3
len_2_63	129459	1			T1	310		T2	1329		T3	17
len_1	32	1			T19	2		T188	1		T189	1