Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	65112950	1			T2	566851		T3	316		T4	1982
all_values[1]	65112950	1			T2	566851		T3	316		T4	1982
all_values[2]	65112950	1			T2	566851		T3	316		T4	1982

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

477450

1

T2

3

T3

14

T4

490

auto[1]

194861400

1

T2

170055

T3

934

T4

5456

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

194476575

1

T2

169014

T3

918

T4

5790

auto[1]

862275

1

T2

10407

T3

30

T4

156

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	148658	1			T4	21		T13	187		T14	162
all_values[0]	auto[0]	auto[1]	1642	1			T4	2		T13	2		T14	2
all_values[0]	auto[1]	auto[0]	64676867	1			T2	563382		T3	306		T4	1909
all_values[0]	auto[1]	auto[1]	285783	1			T2	3469		T3	10		T4	50
all_values[1]	auto[0]	auto[0]	143002	1			T3	11		T4	132		T18	1
all_values[1]	auto[0]	auto[1]	1222	1			T3	3		T4	3		T18	2
all_values[1]	auto[1]	auto[0]	64682523	1			T2	563382		T3	295		T4	1798
all_values[1]	auto[1]	auto[1]	286203	1			T2	3469		T3	7		T4	49
all_values[2]	auto[0]	auto[0]	181655	1			T2	2		T4	327		T14	161
all_values[2]	auto[0]	auto[1]	1271	1			T2	1		T4	5		T14	2
all_values[2]	auto[1]	auto[0]	64643870	1			T2	563380		T3	306		T4	1603
all_values[2]	auto[1]	auto[1]	286154	1			T2	3468		T3	10		T4	47