Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
190612 |
1 |
|
|
T2 |
2 |
|
T3 |
2 |
|
T4 |
66 |
auto[1] |
204584 |
1 |
|
|
T2 |
4672 |
|
T3 |
16 |
|
T4 |
2 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
99392 |
1 |
|
|
T2 |
1176 |
|
T3 |
4 |
|
T4 |
18 |
lower_val |
98199 |
1 |
|
|
T2 |
1197 |
|
T3 |
2 |
|
T4 |
23 |
zero_val |
1408 |
1 |
|
|
T2 |
7 |
|
T3 |
1 |
|
T4 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
197368 |
1 |
|
|
T2 |
2306 |
|
T3 |
10 |
|
T4 |
26 |
lower_val |
197820 |
1 |
|
|
T2 |
2368 |
|
T3 |
8 |
|
T4 |
42 |
zero_val |
8 |
1 |
|
|
T156 |
2 |
|
T157 |
2 |
|
T158 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
23770 |
1 |
|
|
T4 |
8 |
|
T14 |
39 |
|
T16 |
1 |
higher_val |
higher_val |
auto[1] |
25744 |
1 |
|
|
T2 |
598 |
|
T3 |
3 |
|
T13 |
56 |
higher_val |
lower_val |
auto[0] |
24137 |
1 |
|
|
T4 |
9 |
|
T14 |
55 |
|
T17 |
65 |
higher_val |
lower_val |
auto[1] |
25740 |
1 |
|
|
T2 |
578 |
|
T3 |
1 |
|
T4 |
1 |
higher_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T156 |
1 |
|
- |
- |
|
- |
- |
lower_val |
higher_val |
auto[0] |
23610 |
1 |
|
|
T2 |
1 |
|
T4 |
9 |
|
T14 |
53 |
lower_val |
higher_val |
auto[1] |
25413 |
1 |
|
|
T2 |
596 |
|
T3 |
1 |
|
T13 |
35 |
lower_val |
lower_val |
auto[0] |
23792 |
1 |
|
|
T4 |
14 |
|
T14 |
65 |
|
T17 |
83 |
lower_val |
lower_val |
auto[1] |
25382 |
1 |
|
|
T2 |
600 |
|
T3 |
1 |
|
T13 |
30 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T157 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T156 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
538 |
1 |
|
|
T2 |
1 |
|
T4 |
2 |
|
T13 |
1 |
zero_val |
higher_val |
auto[1] |
172 |
1 |
|
|
T2 |
2 |
|
T16 |
1 |
|
T26 |
2 |
zero_val |
lower_val |
auto[0] |
551 |
1 |
|
|
T3 |
1 |
|
T14 |
1 |
|
T17 |
1 |
zero_val |
lower_val |
auto[1] |
147 |
1 |
|
|
T2 |
4 |
|
T4 |
1 |
|
T16 |
1 |