Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	65112950	1			T2	566851		T3	316		T4	1982
all_pins[1]	65112950	1			T2	566851		T3	316		T4	1982
all_pins[2]	65112950	1			T2	566851		T3	316		T4	1982

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	194774073	1			T2	169708		T3	938		T4	5896
values[0x1]	564777	1			T2	3469		T3	10		T4	50
transitions[0x0=>0x1]	563073	1			T2	3469		T3	10		T4	50
transitions[0x1=>0x0]	563096	1			T2	3469		T3	10		T4	50

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	64827167	1			T2	563382		T3	306		T4	1932
all_pins[0]	values[0x1]	285783	1			T2	3469		T3	10		T4	50
all_pins[0]	transitions[0x0=>0x1]	285770	1			T2	3469		T3	10		T4	50
all_pins[0]	transitions[0x1=>0x0]	76	1			T15	5		T41	2		T149	3
all_pins[1]	values[0x0]	65112861	1			T2	566851		T3	316		T4	1982
all_pins[1]	values[0x1]	89	1			T15	5		T41	2		T149	3
all_pins[1]	transitions[0x0=>0x1]	74	1			T15	5		T41	2		T149	3
all_pins[1]	transitions[0x1=>0x0]	278890	1			T24	1071		T25	2701		T26	5706
all_pins[2]	values[0x0]	64834045	1			T2	566851		T3	316		T4	1982
all_pins[2]	values[0x1]	278905	1			T24	1071		T25	2701		T26	5706
all_pins[2]	transitions[0x0=>0x1]	277229	1			T24	1070		T25	2684		T26	5669
all_pins[2]	transitions[0x1=>0x0]	284130	1			T2	3469		T3	10		T4	50