Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
92.59 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv


Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 9 0 9 100.00
Crosses 18 2 16 88.89


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 3 0 3 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=2}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 18 2 16 88.89 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 3 0 3 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 281 1 T116 7 T117 7 T118 4
all_values[1] 281 1 T116 7 T117 7 T118 4
all_values[2] 281 1 T116 7 T117 7 T118 4


Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 449 1 T116 9 T117 11 T118 7
auto[1] 394 1 T116 12 T117 10 T118 5


Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 408 1 T116 7 T117 10 T118 5
auto[1] 435 1 T116 14 T117 11 T118 7


Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 500 1 T116 8 T117 12 T118 9
auto[1] 343 1 T116 13 T117 9 T118 3


Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 18 2 16 88.89 2
Automatically Generated Cross Bins 18 2 16 88.89 2
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Element holes
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTNUMBERSTATUS
[all_values[1]] [auto[0]] * [auto[1]] -- -- 2


Covered bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 75 1 T117 2 T169 3 T170 1
all_values[0] auto[0] auto[0] auto[1] 22 1 T116 1 T171 1 T172 2
all_values[0] auto[0] auto[1] auto[0] 49 1 T116 1 T117 1 T118 2
all_values[0] auto[0] auto[1] auto[1] 23 1 T118 1 T173 2 T170 1
all_values[0] auto[1] auto[0] auto[1] 52 1 T116 2 T117 2 T118 1
all_values[0] auto[1] auto[1] auto[1] 60 1 T116 3 T117 2 T173 1
all_values[1] auto[0] auto[0] auto[0] 73 1 T116 1 T117 1 T118 3
all_values[1] auto[0] auto[1] auto[0] 88 1 T116 2 T117 3 T169 2
all_values[1] auto[1] auto[0] auto[1] 66 1 T116 1 T117 1 T118 1
all_values[1] auto[1] auto[1] auto[1] 54 1 T116 3 T117 2 T169 2
all_values[2] auto[0] auto[0] auto[0] 76 1 T116 2 T117 2 T169 3
all_values[2] auto[0] auto[0] auto[1] 22 1 T117 1 T118 1 T173 1
all_values[2] auto[0] auto[1] auto[0] 47 1 T116 1 T117 1 T169 1
all_values[2] auto[0] auto[1] auto[1] 25 1 T117 1 T118 2 T173 1
all_values[2] auto[1] auto[0] auto[1] 63 1 T116 2 T117 2 T118 1
all_values[2] auto[1] auto[1] auto[1] 48 1 T116 2 T171 1 T174 4


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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