Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	67719827	1			T1	111194		T2	274		T3	159817
all_values[1]	67719827	1			T1	111194		T2	274		T3	159817
all_values[2]	67719827	1			T1	111194		T2	274		T3	159817

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

389430

1

T1

3

T2

67

T3

3

auto[1]

202770051

1

T1

333579

T2

755

T3

479448

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

202232034

1

T1

332460

T2

780

T3

478044

auto[1]

927447

1

T1

1122

T2

42

T3

1407

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	135977	1			T1	1		T13	5		T15	5
all_values[0]	auto[0]	auto[1]	1987	1			T1	2		T13	6		T15	2
all_values[0]	auto[1]	auto[0]	67274701	1			T1	110819		T2	260		T3	159348
all_values[0]	auto[1]	auto[1]	307162	1			T1	372		T2	14		T3	469
all_values[1]	auto[0]	auto[0]	116873	1			T17	1032		T19	6		T38	8
all_values[1]	auto[0]	auto[1]	1335	1			T17	9		T19	5		T38	2
all_values[1]	auto[1]	auto[0]	67293805	1			T1	110820		T2	260		T3	159348
all_values[1]	auto[1]	auto[1]	307814	1			T1	374		T2	14		T3	469
all_values[2]	auto[0]	auto[0]	131826	1			T2	63		T3	2		T14	12
all_values[2]	auto[0]	auto[1]	1432	1			T2	4		T3	1		T14	4
all_values[2]	auto[1]	auto[0]	67278852	1			T1	110820		T2	197		T3	159346
all_values[2]	auto[1]	auto[1]	307717	1			T1	374		T2	10		T3	468