Summary for Variable entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins |
2 |
0 |
2 |
100.00 |
Automatically Generated Bins for entropy_edn_mode_enabled
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
auto[0] |
237916 |
1 |
|
|
T1 |
2 |
|
T2 |
2 |
|
T3 |
620 |
auto[1] |
188500 |
1 |
|
|
T1 |
490 |
|
T2 |
16 |
|
T15 |
16 |
Summary for Variable prescaler_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for prescaler_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
106610 |
1 |
|
|
T1 |
127 |
|
T2 |
5 |
|
T3 |
144 |
lower_val |
105745 |
1 |
|
|
T1 |
110 |
|
T3 |
142 |
|
T13 |
108 |
zero_val |
1440 |
1 |
|
|
T1 |
3 |
|
T2 |
1 |
|
T3 |
3 |
Summary for Variable wait_timer_val
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
User Defined Bins |
3 |
0 |
3 |
100.00 |
User Defined Bins for wait_timer_val
Bins
NAME | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
212864 |
1 |
|
|
T1 |
242 |
|
T2 |
10 |
|
T3 |
302 |
lower_val |
213546 |
1 |
|
|
T1 |
250 |
|
T2 |
8 |
|
T3 |
318 |
zero_val |
6 |
1 |
|
|
T165 |
2 |
|
T166 |
2 |
|
T167 |
2 |
Summary for Cross entropy_timer_cross
Samples crossed: prescaler_val wait_timer_val entropy_edn_mode_enabled
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | MISSING |
Automatically Generated Cross Bins |
18 |
3 |
15 |
83.33 |
3 |
Automatically Generated Cross Bins for entropy_timer_cross
Element holes
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[zero_val] |
[zero_val] |
* |
-- |
-- |
2 |
|
Uncovered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | NUMBER | STATUS |
[higher_val] |
[zero_val] |
[auto[0]] |
0 |
1 |
1 |
|
Covered bins
prescaler_val | wait_timer_val | entropy_edn_mode_enabled | COUNT | AT LEAST | STATUS | | TEST | COUNT | | TEST | COUNT | | TEST | COUNT |
higher_val |
higher_val |
auto[0] |
29687 |
1 |
|
|
T3 |
70 |
|
T13 |
79 |
|
T14 |
99 |
higher_val |
higher_val |
auto[1] |
23600 |
1 |
|
|
T1 |
64 |
|
T2 |
2 |
|
T16 |
63 |
higher_val |
lower_val |
auto[0] |
29651 |
1 |
|
|
T3 |
74 |
|
T13 |
56 |
|
T14 |
100 |
higher_val |
lower_val |
auto[1] |
23670 |
1 |
|
|
T1 |
63 |
|
T2 |
3 |
|
T16 |
66 |
higher_val |
zero_val |
auto[1] |
2 |
1 |
|
|
T166 |
1 |
|
T167 |
1 |
|
- |
- |
lower_val |
higher_val |
auto[0] |
29283 |
1 |
|
|
T1 |
1 |
|
T3 |
75 |
|
T13 |
53 |
lower_val |
higher_val |
auto[1] |
23450 |
1 |
|
|
T1 |
51 |
|
T15 |
1 |
|
T16 |
94 |
lower_val |
lower_val |
auto[0] |
29415 |
1 |
|
|
T3 |
67 |
|
T13 |
55 |
|
T14 |
89 |
lower_val |
lower_val |
auto[1] |
23595 |
1 |
|
|
T1 |
58 |
|
T15 |
2 |
|
T16 |
74 |
lower_val |
zero_val |
auto[0] |
1 |
1 |
|
|
T165 |
1 |
|
- |
- |
|
- |
- |
lower_val |
zero_val |
auto[1] |
1 |
1 |
|
|
T166 |
1 |
|
- |
- |
|
- |
- |
zero_val |
higher_val |
auto[0] |
561 |
1 |
|
|
T1 |
1 |
|
T2 |
1 |
|
T16 |
1 |
zero_val |
higher_val |
auto[1] |
156 |
1 |
|
|
T1 |
2 |
|
T17 |
1 |
|
T42 |
1 |
zero_val |
lower_val |
auto[0] |
579 |
1 |
|
|
T3 |
3 |
|
T13 |
1 |
|
T14 |
1 |
zero_val |
lower_val |
auto[1] |
144 |
1 |
|
|
T17 |
2 |
|
T42 |
1 |
|
T88 |
3 |