Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	3	0	3	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	67719827	1			T1	111194		T2	274		T3	159817
all_pins[1]	67719827	1			T1	111194		T2	274		T3	159817
all_pins[2]	67719827	1			T1	111194		T2	274		T3	159817

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	202543652	1			T1	333210		T2	808		T3	478982
values[0x1]	615829	1			T1	372		T2	14		T3	469
transitions[0x0=>0x1]	613974	1			T1	372		T2	14		T3	469
transitions[0x1=>0x0]	613999	1			T1	372		T2	14		T3	469

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	67412665	1			T1	110822		T2	260		T3	159348
all_pins[0]	values[0x1]	307162	1			T1	372		T2	14		T3	469
all_pins[0]	transitions[0x0=>0x1]	307154	1			T1	372		T2	14		T3	469
all_pins[0]	transitions[0x1=>0x0]	92	1			T152	4		T180	5		T181	2
all_pins[1]	values[0x0]	67719727	1			T1	111194		T2	274		T3	159817
all_pins[1]	values[0x1]	100	1			T152	4		T180	5		T181	2
all_pins[1]	transitions[0x0=>0x1]	88	1			T152	4		T180	5		T181	2
all_pins[1]	transitions[0x1=>0x0]	308555	1			T17	10226		T23	1040		T24	1318
all_pins[2]	values[0x0]	67411260	1			T1	111194		T2	274		T3	159817
all_pins[2]	values[0x1]	308567	1			T17	10226		T23	1040		T24	1318
all_pins[2]	transitions[0x0=>0x1]	306732	1			T17	10155		T23	1040		T24	1318
all_pins[2]	transitions[0x1=>0x0]	305352	1			T1	372		T2	14		T3	469