Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	7	0	7	100.00
Crosses	12	0	12	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	3	0	3	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=2}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	12	0	12	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	67416218	1			T1	2394		T2	21167		T3	168478
all_values[1]	67416218	1			T1	2394		T2	21167		T3	168478
all_values[2]	67416218	1			T1	2394		T2	21167		T3	168478

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

563151

1

T1

302

T2

419

T3

1212

auto[1]

201685503

1

T1

6880

T2

63082

T3

504222

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

201335604

1

T1

7110

T2

62865

T3

504948

auto[1]

913050

1

T1

72

T2

636

T3

486

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	12	0	12	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	171129	1			T1	294		T2	67		T13	286
all_values[0]	auto[0]	auto[1]	1826	1			T1	6		T2	2		T13	2
all_values[0]	auto[1]	auto[0]	66940739	1			T1	2076		T2	20888		T3	168316
all_values[0]	auto[1]	auto[1]	302524	1			T1	18		T2	210		T3	162
all_values[1]	auto[0]	auto[0]	186602	1			T1	1		T2	345		T3	605
all_values[1]	auto[0]	auto[1]	1402	1			T2	5		T3	1		T13	2
all_values[1]	auto[1]	auto[0]	66925266	1			T1	2369		T2	20610		T3	167711
all_values[1]	auto[1]	auto[1]	302948	1			T1	24		T2	207		T3	161
all_values[2]	auto[0]	auto[0]	200664	1			T1	1		T3	605		T13	294
all_values[2]	auto[0]	auto[1]	1528	1			T3	1		T13	3		T16	7
all_values[2]	auto[1]	auto[0]	66911204	1			T1	2369		T2	20955		T3	167711
all_values[2]	auto[1]	auto[1]	302822	1			T1	24		T2	212		T3	161